Wednesday, 20 February 2013

Start to build the Oscilloscope + FPGA block diagram

I started to build the oscilloscope. I tested the 3V analog, the 1.2V digital, the 3.3V digital. and they seems OK. I'm waiting some components, tomorrow I should be able to test the -5V and check the susceptibility on the 5V analog as well. Each amplification stage can be powered individually, so if there is a fault on the board it should be easily fixed. I believe in the next 2 days I should manage to assemble the board.

It would be nice to be so proficient at  work, unfortunately I'm tagged as "digital" designer and I can only do 30% of what I could...I get very frustrated for that... well... life is too short to get too upset I guess...

FPGA Block diagram

The above is the FPGA block diagram. The FPGA has got an UART to communicate externally with an FTDI chip or a wiznet. the RX_UART (uups I wrote TX_UART above) send the received data to the interpreter which decode the input and drive the trigger unit, the AC_DC relay or the attenuator.
on the TX side the trigger unit gets the CH1, CH2 data, and accordingly to the command received from the INTERPRETER trigger CH1 or CH2. data are then send to a module that I call TX_CPU, and finally sent to the UART_TX.

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